Due to a problem in the O-RAN Intel® FPGA IP version 1.6.0 and earlier, you may see the O-RAN Intel FPGA IP gives incorrect values when Block floating-point compression is turned on.
When the original PRB value is almost saturated at maximum positive value, O-RAN intel FPGA IP may generate a negative value of compressed PRB.
For example, the original PRB value “8180” is compressed to 9 bits using the exponent value `5` and the compressed PRB value is incorrectly generated as 256 (0x100). The compressed value is expected to be decompressed as 16-bits and the expected value is 8192 (0x2000). However, the decompressed outcome becomes 8192(0xE000).
This problem impacts the IqWidth from `8` to `15`.
The Fronthaul Compression Intel® FPGA IP has the same problem.
This problem is fixed starting with the O-RAN Intel® FPGA IP and the Fronthaul Compression Intel FPGA IP webcore version 22.2.