Article ID: 000091371 Content Type: Errata Last Reviewed: 06/30/2022

Why do I see link up issues when using the F-Tile Serial Lite IV Intel® FPGA IP FHT PMA variants at NRZ F50G and PAM4 F100G?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Interfaces
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2, you may encounter link up issues when using the F-Tile Serial Lite IV Intel® FPGA IP FHT PMA variants at NRZ F50G and PAM4 F100G when running the design example system console TCL.

    Resolution

     

    To work around this problem in the Intel® Quartus® Prime Pro Edition software version 22.2, after generating the F-Tile Serial Lite IV Intel® FPGA IP Design Example, replace the lanes calculation expression as shown below in the ed_hwtest/system_console/sliv_ftile.tcl file.

     

    FHT NRZ 48G-58G:

    proc wait_for_pcs_ready { } {

    Line 201 : set actual_lane  $lanes → set actual_lane [expr $lanes >> 1]

    }

    proc sl4_link_init_int_lpbk {val} {

    Line 1071 : set real_lanes $lanes → set real_lanes [expr $lanes >> 1]

    }

     

    FHT PAM4 96G-116G:

    proc wait_for_pcs_ready { } {

    Line 199:  set actual_lane [expr $lanes >> 1] → set actual_lane [expr $lanes >> 2]

    }

    proc sl4_link_init_int_lpbk {val} {

    Line 1068: set real_lanes [expr $lanes >> 1] → set real_lanes [expr $lanes >> 2]

    }

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs

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