Article ID: 000091368 Content Type: Errata Last Reviewed: 06/30/2022

Why is there intermittent link up issue after changing the loopback mode of the F-Tile Serial Lite IV Intel® FPGA IP system console design example?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Interfaces
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2, you may see the intermittent link-up issue after changing the loopback mode on the F-Tile Serial Lite IV Intel® FPGA IP System Console design example when running at 1Gbps datarate.

    Resolution

    To work around this problem in the Intel® Quartus® Prime Pro Edition Software version 22.2, generate the F-Tile Serial Lite IV Hardware Test Design Example and insert "after 10000" at line 225 in the ed_hwtest/system_console/sliv_ftile.tcl file.   

    Example sliv_ftile.tcl after fix on Line 224 to 226:
    ...
    sys_reset
    after 10000
    }

    ...

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.
     

     

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs

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