Article ID: 000091353 Content Type: Troubleshooting Last Reviewed: 07/07/2022

Why does the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* fails to simulate when using the Synopsys* VCS*/VCS MX* simulator?

Environment

  • Intel® Quartus® Prime Pro Edition
  • OS Independent family

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    Description

    Due to a problem in the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express*, you may observe an error message saying simulation stopped due to inactivity when using the Synopsys* VCS*/VCS MX* simulator.

    Resolution

    To work around this problem, when starting the simulation, execute the following command: 
    sh vcs_setup.sh USER_DEFINED_COMPILE_OPTIONS="" USER_DEFINED_ELAB_OPTIONS="-xlrm\ uniq_prior_final\ -debug_access+all" USER_DEFINED_SIM_OPTIONS="" TOP_LEVEL_NAME="pcie_ed_tb" | tee simulation.log

     

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs I-Series

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