Due to a problem in the Intel® Quartus® Prime Pro Edition Software Version 22.2, the E-Tile Hard IP for Ethernet Intel® FPGA IP generated Design Example with selected QSYS as the design environment mode may fail to compile and simulate with the following error message. You may see failure in hardware for the QSYS mode design example that can be compiled successfully. The error messages vary based on IP settings.
Example of Intel® Quartus® Prime Pro compilation error and warning message:
- Error (13458): Verilog HDL Continuous Assignment error at alt_ehipc3_hw.v(423): object "o_sl_tx_ready_1" on left-hand side of assignment must have a net type
- Error(129001): Input port REFCLK on atom "iopll_sclk_todsync_inst|altera_iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll", which is a fourteennm_iopll primitive, is not legally connected and/or configured
- Warning(16788): Net "i_clk_ref_0" does not have a driver at alt_ehipc3_hw.v(260)
- Warning(16788): Net "i_sl_clk_tx_0" does not have a driver at alt_ehipc3_hw.v(272)
Example of simulation error message:
- Error (suppressible): ./basic_avl_tb_top.sv(175): (vopt-2912) Port 'i_clk_ref' not found in module 'ex_25G' (1st connection)
- Error (suppressible): ./basic_avl_tb_top.sv(196): (vopt-2912) Port 'i_sl_clk_tx' not found in module 'ex_25G' (3rd connection)
To work around this problem in the Intel® Quartus® Prime Pro Edition Software v22.2, generate the design example in NATIVE Design Environment mode.
This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.
