Article ID: 000091267 Content Type: Troubleshooting Last Reviewed: 08/15/2022

Why do I get an error related to bit range while using Intel® Agilex™ Advanced SEU Detection (ASD) IP?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Advanced SEU Detection Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The total CRAM sector range for Intel® Agilex™ devices is from 0-4159 (0X103F), while the maximum bit covered in ASD IP is 4095 (0xFFF). The current ASD IP bit range (12 bits) is not sufficient to cover all the bit positions within the frame for the affected Intel® Agilex™ devices.

    As a result, an inaccurate report is shown (0x000-0x03F) when the SEU event happens within the bit range 4096-4159. When the error reporting value is between 0x000-0x03F, the bit range affected could be from 0-63 or 4096-4159. This issue also affects the Fault Injection Debugger Tool.

    However, SEU detection and correction are still working fine for the entire bit position.

     

     

    Resolution

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs

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