The total CRAM sector range for the Intel Agilex® 7 FPGAs is from 0-4159 (0X103F), while the maximum bit covered in Advanced SEU Detection Intel® FPGA IP is 4095 (0xFFF). The current Advanced SEU Detection Intel® FPGA IP bit range (12 bits) is insufficient to cover all the bit positions within the frame for the affected Intel Agilex® 7 FPGAs.
As a result, an inaccurate report is shown (0x000-0x03F) when the SEU event happens within the bit range 4096-4159. When the error reporting value is between 0x000-0x03F, the bit range affected could be from 0-63 or 4096-4159. This problem also affects the Fault Injection Debugger Tool.
However, SEU detection and correction are still working fine for the entire bit position.
This problem has been fixed in the Intel® Quartus® Prime Pro Edition Software v23.1