If you are using the Avalon® streaming x16 or Avalon streaming x32 configuration mode on Intel Agilex® 7 F-Series 019/023, Intel Agilex® 7 I-Series 019/023, and future devices, there are dual-purpose pins usage restrictions to eliminate the need to power cycle the FPGA when the FPGA enter the rare unrecoverable error state.
Refer to the following table for dual-purpose pins restrictions for Avalon streaming x16 or x32 configuration scheme.
| Dual-Purpose Pins | Avalon® streaming x16 | Avalon streaming x32 | ||
| Not Used in User Mode | Used in User Mode | Not Used in User Mode | Used in User Mode | |
| AVST_CLK | Setting: As input tri-stated | Setting: Use as regular I/O Pin connection: Used as input and assign ALL pins in pin assignment. | Setting: As input tri-stated | Setting: Use as regular I/O Pin connection: Used as input and assign ALL pins in pin assignment. |
| AVST_VALID | ||||
| AVST_DATA[15:0] | ||||
| AVST_DATA[31:16] | No restriction; can be any setting. | |||
Notes:
1. All pins in the same group name must be assigned to the physical pin in the pin assignment. For instance, if only 2 out of 16 pins from AVST_data[15:0] pins are used, all 16 pins must be assigned to the physical pins, including the unused pins in the user design.
2. All pins assigned in pin assignment must be in a known state, either weak pull-up or pull-down.
3. This restriction is not applicable to Intel Agilex® 7 F-Series 012/014/022/027 and Intel Agilex® 7 I-Series 022/027 devices.
Above information can also be found in Intel Agilex® Configuration User Guide.