Due to the problem with the subcomponent of On-chip Memory II (RAM or ROM) Intel FPGA IP introduced in Quartus® Prime Pro Edition Software version 21.4, when you enable the In-System Memory Content Editor feature inside On-chip Memory II (RAM or ROM) Intel FPGA IP, all read from offset 0x00 using On-chip Memory II (RAM or ROM) Intel FPGA IP Avalon-MM slave port will be invalid. The returned data will be the same as data from the previous transaction.
To work around this problem, uncheck Enable In-System Memory Content Editor feature in the On-chip Memory II (RAM or ROM) Intel FPGA IP parameters editor. If you need to read or edit memory content, connect JTAG to Avalon Master Bridge Intel FPGA IP to the Avalon-MM slave port on the On-chip Memory II (RAM or ROM) Intel FPGA IP. Then you can use System Console to interface memory content for debug purposes.