Article ID: 000091170 Content Type: Error Messages Last Reviewed: 06/30/2022

Error(19261): Signal pcie_rstn_pin_perst has been constrained to a location that is a dual purpose pin that can be used by the PCIe HIP as nPERST.

Environment

  • Intel® Quartus® Prime Pro Edition
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The following error will be seen when compiling a design that includes the Intel® Stratix® 10 Hard IP for PCI Express targeting an 1SG040* device OPN.
    The nPERSTL0 pin of this device package is a dual purpose and located in a 3.0 V bank.

    Error(19261): Signal pcie_rstn_pin_perst has been constrained to a location that is a dual purpose pin that can be used by the PCIe HIP as nPERST.

    Resolution

    When using this pin as PCI Express nPERST with I/O standards of 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.0 V LVTTL, the following assignment should be added in the Intel® Quartus® Prime Software settings file (.qsf) to disable GPIO usage and to resolve the error.
    set_instance_assignment -name USE_AS_3V_GPIO ON -to pin_name

    Example:
    set_instance_assignment -name USE_AS_3V_GPIO ON -to pcie_rstn_pin_perst

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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