Article ID: 000091149 Content Type: Troubleshooting Last Reviewed: 11/14/2024

Why does Fixed Point Dedicated Pre Adder with sub direction is not inferred for unsigned multiplier inputs?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Multiply Adder Intel® FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    This problem can be seen when using Multiply Adder FPGA IP with the following settings:

    • Preadder direction set to SUB
    • Multiplier inputs set to UNSIGNED  

    This is due to multiplier inputs must be signed when the preadder is performing subtraction.

     

     

    Resolution

    To avoid this problem, ensure that multiplier inputs are set to SIGNED when using SUB preadder direction.

     

     

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices

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