Error (13452): Verilog HDL Module Instantiation error: module "altera_emif_arch_nd_bufs" has no parameter named "PORT_MEM_CK_BIDIR_WIDTH"

Due to a problem in the Quartus® Prime Pro Edition Software v22.1 and earlier,  you might see this error after upgrading the External Memory Interfaces Stratix® 10 FPGA IP core from a previous Quartus® Prime Pro Edition Software version.

The error occurs when a design contains more than one instance of the External Memory Interfaces Stratix® 10 FPGA IP core, and not all have been upgraded to the same version of the Quartus® Prime Pro Edition Software.

To work around this problem, upgrade all instances of the External Memory Interfaces Stratix® 10 FPGA IP core to the same version of the Quartus® Prime Pro Edition Software.