Article ID: 000091063 Content Type: Error Messages Last Reviewed: 06/15/2022

Error (13452): Verilog HDL Module Instantiation error: module "altera_emif_arch_nd_bufs" has no parameter named "PORT_MEM_CK_BIDIR_WIDTH"

Environment

  • Intel® Quartus® Prime Pro Edition
  • External Memory Interfaces Intel® Stratix® 10 FPGA IP
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    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software v22.1 and earlier,  you might see this error after upgrading the External Memory Interfaces Intel® Stratix® 10 FPGA IP core from a previous Intel® Quartus® Prime Pro Edition Software version.

    The error occurs when a design contains more than one instance of the External Memory Interfaces Intel® Stratix® 10 FPGA IP core and not all have been upgraded to the same version of the Intel® Quartus® Prime Pro Edition Software.

    Resolution

    To work around this problem, upgrade all instances of the External Memory Interfaces Intel® Stratix® 10 FPGA IP core to the same version of the Intel® Quartus® Prime Pro Edition Software.
    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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