Article ID: 000091014 Content Type: Troubleshooting Last Reviewed: 02/15/2023

Why does the Hard IP Reconfiguration Interface deadlock when using the P-Tile Intel® FPGA IP for PCI Express*?

Environment

    Intel® Quartus® Prime Pro Edition
    Interfaces
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Description

Due to a limitation in the P-Tile Intel® FPGA IP for PCI Express* with the Intel® Quartus® Prime Pro Edition Software version 22.2 and earlier version, the Hard IP Reconfiguration Interface can deadlock with "hip_reconfig_waitrequest_o" asserted. The problem cannot be resolved by resetting the P-Tile Intel® FPGA IP for PCI Express* using the "pin_perst_n".

Resolution

To avoid this problem, ensure that the Hard IP Reconfiguration Interface is not used during the assertion of "pin_perst_n".

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 22.3. 

Related Products

This article applies to 2 products

Intel Agilex® 7 FPGAs and SoC FPGAs F-Series
Intel® Stratix® 10 DX FPGA

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