Article ID: 000091014 Content Type: Troubleshooting Last Reviewed: 06/30/2022

Why does the Hard IP Reconfiguration Interface deadlock when using the P-Tile Intel® FPGA IP for PCI Express*?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Interfaces
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a limitation in the P-Tile Intel® FPGA IP for PCI Express* with the Intel® Quartus® Prime Pro Edition Software version 21.4, the Hard IP Reconfiguration Interface can deadlock with "hip_reconfig_waitrequest_o" asserted. The issue can't be resolved by resetting the P-Tile Intel® FPGA IP for PCI Express* using the "pin_perst_n".

    Resolution

    To avoid this issue, ensure that the Hard IP Reconfiguration Interface is not used during the assertion of "pin_perst_n".

    The limitation will be fixed in a future version of the Intel® Quartus® Prime Pro Edition Software. 

    Related Products

    This article applies to 2 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs F-Series
    Intel® Stratix® 10 DX FPGA

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