Article ID: 000091012 Content Type: Troubleshooting Last Reviewed: 06/30/2022

Why is RxErr status asserted after asserting the ports "pld_clrpcs_n[1:0]" while using the P-Tile Intel® FPGA IP for PCI Express?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Interfaces
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The RxErr status will be asserted after reseting the P-Tile Intel® FPGA IP for PCI Express with the pld_clrpcs_n[1:0] ports.

    Resolution

    According to the PCI Express Base specification revision 4.0 version 1.0, sticky registers including RxErr status are not cleared after any type of conventional reset (cold, warm, or hot).

    Clear the RxErr status in PCI Express configuration space register before checking the RxErr status during data transaction.

    This behaviour will not be changed in a future release of the Intel® Quartus® Prime Pro Edition Software.   

    Related Products

    This article applies to 2 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs F-Series
    Intel® Stratix® 10 DX FPGA

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