Article ID: 000090985 Content Type: Errata Last Reviewed: 04/03/2023

Why does the transaction pending bit remain asserted for virtual functions while using the P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express?


  • Intel® Quartus® Prime Pro Edition
  • Interfaces
  • Apple family*


    Due to a known problem detailed in the Intel Agilex® 7 ES Device Errata Sheet and User Guidelines (ES-1069). When using the P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express, with the multi-function feature enabled, the PCI Express device status register (offset 0x07Ah bit [5]: Transactions pending bit) for each of the virtual functions (VF) is implemented as a Write-1-to-Clear status register (RW1C). The PCI Express Base specification revision 4.0 version 1.0 states that this register must be implemented as read-only (RO) when multi-function feature is enabled. This problem does not cause functional failures.


    There is no plan to fix this problem. To work around this problem, the application logic can use Configuration Intercept Interface (CII) or Direct User Avalon® Memory-Mapped Interface to modify the configuration accesses to this register.

    Related Products

    This article applies to 2 products

    Intel® Stratix® 10 DX FPGA
    Intel Agilex® 7 FPGAs and SoC FPGAs F-Series