Due to a known issue detailed in the Intel® Agilex™ ES Device Errata Sheet and User Guidelines (ES-1069). When using the P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express, with the multi-function feature is enabled, the PCI Express device status register (offset 0x07Ah bit [5]: Transactions pending bit) for each of the virtual functions (VF) is implemented as a Write-1-to-Clear status register (RW1C). The PCI Express Base specification revision 4.0 version 1.0, states that this register must be implemented as read-only (RO) when multi-function feature is enabled. This issues does not cause functional failures.
No planned fix for this issue. The application logic can use Configuration Intercept Interface (CII) or Direct User Avalon® Memory-Mapped Interface to modify the configuration accesses to this register.
