The Avalon® Memory Mapped or AXI host may hang while issuing read-or-write requests to the Avalon Memory Mapped or AXI agent within 16 clock cycles of the reset being de asserted.
Ensure that all the components in the interconnect assert the reset for at least 16 cycles and start transactions 16 cycles after the de-assertion of the reset. This period allows all the IP components to reset and come out of the reset state. For more information, refer to the Intel® Quartus® Prime Pro Edition User Guide: Platform Designer. Section 6 Platform Designer Interconnect, Synchronous Reset Support.