Article ID: 000090687 Content Type: Errata Last Reviewed: 05/10/2022

Why do I see both compilation failures and functional problems when using multiple instantiations of the Interlaken (2nd Generation) Intel® FPGA IP core with different configurations in the Intel® Quartus® Prime Pro Edition Software?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Interlaken (2nd Generation) Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 20.2 and earlier, instantiating different configurations of the Interlaken (2nd Generation) Intel® FPGA IP core in your design may encounter problems. The file uflex_ilk_dcore.sv is not unique to each configuration of the intellectual property (IP) and this can cause compilation and functional problems.

    Resolution

    To work around this problem in the Intel® Quartus® Prime Pro Edition Software version 20.2 and earlier, uniquify the file uflex_ilk_dcore.sv for each configuration of the Interlaken (2nd Generation) Intel® FPGA IP core to be used.

    This problem has been fixed starting with the Intel® Quartus® Prime Pro Edition Software version 20.3.

    Related Products

    This article applies to 2 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs
    Intel® Stratix® 10 FPGAs and SoC FPGAs

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