Error: Internal error: standard logic: Zero or negative width types not supported, it was -1

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1, you may see this error when performing Generate HDL in Platform Designer. The reason for this error is that dynamic port widths have been defined in the GLOBAL section of the _hw.tcl file:

add_parameter AVS_ADDR_WIDTH INTEGER 36

set_parameter_property AVS_ADDR_WIDTH DERIVED true

set_parameter_property AVS_ADDR_WIDTH VISIBLE false

set_parameter_property AVS_ADDR_WIDTH AFFECTS_GENERATION false

set_parameter_property AVS_ADDR_WIDTH HDL_PARAMETER false

add_interface_port avs0 avs0_address address Input AVS_ADDR_WIDTH

To work around this problem, either replace the dynamic port width definition with a constant value:

add_parameter AVS_ADDR_WIDTH INTEGER 36

set_parameter_property AVS_ADDR_WIDTH DERIVED true

set_parameter_property AVS_ADDR_WIDTH VISIBLE false

set_parameter_property AVS_ADDR_WIDTH AFFECTS_GENERATION false

set_parameter_property AVS_ADDR_WIDTH HDL_PARAMETER false

add_interface_port avs0 avs0_address address Input 36

or define the dynamic port width in the ELABORATION section of the _hw.tcl file.

This problem is fixed starting with the Intel® Quartus® Prime software version 22.3