Article ID: 000090313 Content Type: Error Messages Last Reviewed: 04/06/2022

Why is an unconstrained clock error reported when using the Error Message Register Unloader Intel® FPGA IP?

Environment

  • Intel® Quartus® Prime Standard Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Standard Edition Software version 20.1 and later,  an unconstrained clock is reported in the check timing report in the Timing Analyzer as shown below when using the Error Message Register Unloader Intel® FPGA IP. This problem occurs on Cyclone® V FPGAs.

    emr_unloader_component|current_state.STATE_CLOCKHIGH ; Node was determined to feed a clock port but was found without an associated clock assignment. 

    emr_unloader_component|crcblock_atom:emr_atom|generate_crcblock_atom.emr_atom~FF_** ; No clock feeds this register's clock port.

    Resolution

    To work around this problem, add the create_generated_clock  constraint to your SDC file.

    For example:

    create_generated_clock -name emr_unloader_STATE_CLOCKHIGH -source [get_ports {<clock name>}] [get_keepers {<path to IP>|EMR_unloader0:inst|EMR_unloader0_emr_unloader2_0:emr_unloader2_0|altera_emr_unloader:emr_unloader_component|current_state.STATE_CLOCKHIGH}]

     

     

    Related Products

    This article applies to 1 products

    Cyclone® V FPGAs and SoC FPGAs

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.