Article ID: 000090281 Content Type: Troubleshooting Last Reviewed: 05/09/2022

Why are XTS data packets corrupted during interleaving of GCM and XTS profiles when using the Symmetric Cryptographic Intel® FPGA Hard IP?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Interfaces
  • OS Independent family

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    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.4 and later, XTS data packets can be corrupted when keys and data are interleaved independently across channels during interleaving of GCM and XTS profiles when using the Symmetric Cryptographic Intel® FPGA Hard IP.

    Resolution

    Workaround for 1x512-bit mode:

    Program data with keys before interleaving and send a minimum of one data cycle with every key programming cycle.

    Resolution for 2x256-bit mode:

    Support for 2x 256-bit mode has been removed from the Intel® Quartus® Prime Pro Edition Software version 22.1 and later.

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs

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