Error(13224): Verilog HDL or VHDL error at <your module name>.sv(<your line number>): index <your index> is out of range [<your range>] for '<your variable>'

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.4 and earlier, you may see this error during the Analysis & Synthesis stage. This is due to the parameterized interfaces' failure to override the SystemVerilog interface localparam logic variables with the top-level wrapper variables.

In the example below, the interface localparam logic variables ADDR_W and DATA_W, with the parameters of 4 and 1, are not overridden by the top-level wrapper variables, with the parameters of 5 and 8 respectively.  

Top-level wrapper:

module mem_wrapper #( int ADDR_W = 5, int DATA_W = 8 )

...

    mem_if #( ADDR_W, DATA_W ) mem_if ( i_clk_a );

    mem mem ( mem_if );

...

endmodule : mem_wrapper

Interface:

interface mem_if #( int ADDR_W = 4, int DATA_W = 1 ) ( input clk );

    localparam logic [DATA_W - 1:0] INIT_V [2 ** ADDR_W] = '{default: '1};

...

    modport mem ( input clk, addr, wren, idat, output odat );

endinterface : mem_if

Modport:

module mem ( mem_if.mem mem_if );

   logic [mem_if.DATA_W - 1:0] mem [2 ** mem_if.ADDR_W];

   initial
     for(int i = 0; i < 2 ** mem_if.ADDR_W; i++)
       mem[i] = mem_if.INIT_V[i];

...

endmodule : mem

To avoid this error, do not use the localparam logic in the SystemVerilog interface.

For example:

Interface:

interface mem_if #( int ADDR_W = 4, int DATA_W = 1 ) ( input clk );

    logic [DATA_W - 1:0] INIT_V [2 ** ADDR_W] = '{default: '1};

...

    modport mem ( input clk, addr, wren, idat, output odat, INIT_V);

endinterface : mem_if

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 22.4.