Why are there simulation errors when using the Intel Agilex® 7 FPGA R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example testbench using the Cadence Xcelium* simulator?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.4 and earlier, you might encounter the following error:

xmelab: *F,CUMSTS: Timescale directive missing on one or more modules.
xmsim: 20.03-s005: (c) Copyright 1995-2020 Cadence Design Systems, Inc.
xmsim: *F,NOSNAP: Snapshot 'pcie_ed_tb.pcie_ed_tb' does not exist in the libraries.

This problem has been fixed in the Intel® Quartus® Prime Pro Edition Software version 22.3.
Note: The Xcelium simulator support is only available in devices with the suffix R2 or R3 in their ordering part numbers (OPNs).