Article ID: 000090135 Content Type: Troubleshooting Last Reviewed: 05/03/2022

Why does my Intel® Agilex™ device appear as an unknown device in the JTAG chain?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

During power up of an Intel® Agilex™ device, if there is an offset voltage on VCCBAT between 60mV* and 225 mV before it is powered on, the device may enter a test mode, preventing successful configuration.

To verify if this affects you, test or check the following behaviors:

 

  1. Use jtagconfig --debug in a console. The IDCODE will not be read properly and the capture Instruction Register (IR) after device is out of reset will be 88bit in length. The length may vary if there is more than 1 device in the chain.
  2. Scope nSTATUS, VCCIO_SDM, VCCPT and VCCL_SDM. nSTATUS will be pulled low unintentionally when VCCIO_SDM is ramping up
  3. The time between VCCBAT ramping up to nSTATUS being asserted is approximately 6.2ms
Resolution

To work around this issue you can try to implement one of the following recommendations in the short term:

  • Add sufficient bulk capacitors allowed by VCCBAT’s VRM to reduce the offset voltage below 50mV* or 60mV*.
  • Add a pull-down resistor on VCCBAT rail to reduce the offset voltage below 50mV* or 60mV*.

 

For a long term solution refer to the latest Intel® Agilex™ Device Family Pin Connection Guidelines

 

*Note:

- 50mV for operating temperature below 0°C (Industrial Grade)

- 60mV for operating temperature above 0°C(Extended Grade)

Related Products

This article applies to 1 products

Intel® Agilex™ 7 FPGAs and SoC FPGAs

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