Article ID: 000090107 Content Type: Product Information & Documentation Last Reviewed: 03/24/2022

Can I drive the Intel® Cyclone® 10 GX device transceiver pins during power-up and power-down sequencing?

Environment

  • Transceiver Native PHY Intel® Arria® 10 Cyclone® 10 FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    No, you cannot drive the Intel® Cyclone® 10 GX device transceiver pins during power-up and power-down sequencing even if the signal is less than 1.1 Vp-p.

    You may only drive the Intel® Cyclone® 10 GX device transceiver pins with 0V or tristate during power-up or power-down sequencing.

    Resolution

    Table 99. Pin Tolerance - Power-Up/Power-Down of the Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook will be updated in future versions.

    Related Products

    This article applies to 1 products

    Intel® Cyclone® 10 GX FPGA

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