Article ID: 000090104 Content Type: Troubleshooting Last Reviewed: 03/23/2022

Why does my gate level simulation not match my RTL simulation in some cases of inferred RAMs with the combination of registered write-address and registered memory output?

Environment

  • Intel® Quartus® Prime Pro Edition
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    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.4 and earlier, you might see the gate level simulation of your M20K RAM is functionally incorrect while performing simultaneous read and write (Read-during-write (RDW)) of the memory.

    Resolution

    To work around this problem, perform either one of these steps:

    • Implement the RAM in MLABs or logic 
    • Avoid performing RDW operations

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices

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