Article ID: 000090027 Content Type: Product Information & Documentation Last Reviewed: 08/23/2023

Why do I see RTS and CTS signal in U-boot when using both UART0 and I2C1 on the same pin with Auto Flow control disabled on Cyclone® V SoCs?

Environment

  • Intel® Quartus® Prime Design Software
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When using UART0 and I2C1 on Cyclone® V SoCs, you might observe that the msr.dcts register value changed in U-boot with Automatic Flow Control disabled in your Platform Designer system when reading or writing using I2C.

    Resolution

    The changed in msr.dcts register value can be safely ignored. 

    Related Products

    This article applies to 2 products

    Cyclone® V FPGAs and SoC FPGAs
    Cyclone® V Development Kits

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