Article ID: 000089972 Content Type: Troubleshooting Last Reviewed: 01/28/2023

Why am I unable to set the 'Size of address pages' to a value between 17 and 21 bits for the Intel® Arria® 10 FPGA and Intel® Cyclone® 10 GX FPGA Hard IP for PCI Express in Avalon® memory-mapped mode?

Environment

    Intel® Quartus® Prime Standard Edition
    Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
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Description

Due to a problem in the Intel® Quartus® Prime Standard Edition Software version 18.1 and later, address page sizes between 17 and 21 bits (inclusive) are not available for selection when using the Intel® Arria® 10 FPGA and Intel® Cyclone® 10 GX FPGA Hard IP for PCI Express in Avalon® memory-mapped mode with Avalon memory-mapped address width of 32 bits.

Resolution

This problem is fixed starting with the Intel® Quartus® Prime Standard Edition Software version 22.1.

Related Products

This article applies to 2 products

Intel® Arria® 10 FPGAs and SoC FPGAs
Intel® Cyclone® 10 GX FPGA

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