Article ID: 000089968 Content Type: Troubleshooting Last Reviewed: 04/06/2022

Why do I see a “rx_dpa_hold” pin when “RX SOF-CDR” mode is selected in Intel® Stratix® 10 FPGA LVDS SERDES IP?

Environment

  • Intel® Quartus® Prime Pro Edition
  • LVDS SERDES Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in Intel® Quartus® Prime Pro Edition Software version 21.3 and above, you can generate and compile a design with the  Intel® Stratix® 10 FPGA LVDS SERDES IP with the rx_dpa_hold pin when the RX SOF-CDR mode is selected.

    Resolution

    You may ignore the rx_dpa_hold pin and leave it unconnected.

    This problem is scheduled to be fixed in future release of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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