Article ID: 000089642 Content Type: Troubleshooting Last Reviewed: 04/28/2022

Why can’t I reset the Hard Processor System (HPS) of Intel® Agilex™ FPGA or Intel® Stratix® 10 FPGA using the Mailbox Client Intel® FPGA IP?


  • Intel® Quartus® Prime Pro Edition

    You may see the Hard Processor System (HPS) on Intel® Agilex™ SoC FPGA and Intel® Stratix® 10 SoC FPGA fail to reset when issuing the REBOOT_HPS command (0x47) from Linux through the Mailbox Client Intel FPGA IP. 

    The REBOOT_HPS command is not supported by the FPGA Core / Secure Device Manager (SDM) interface, trying to reset the HPS from the FPGA core will be unsuccessful.




    To work around this problem, you must issue the command to reset the HPS through the JTAG interface using the System Console packet service as described in AN 936: Executing SDM Commands via JTAG Interface

    1. Extract the contents of the

    2. Open System Console from the Intel Quartus Prime Pro Software by clicking Tools -> System Debugging Tools -> System Console

    3. In the terminal window of System Console, change directories to where the file sdm_command.tcl was extracted.

    4. Enter the command:
      % source sdm_command.tcl

    5. Execute the REBOOT_HPS command (0x47) with the exec_command procedure:
      % exec_command 0x47

    The Intel Agilex Hard Processor Technical Reference Manual and  Intel Stratix 10 Hard Processor System Technical Reference Manual are scheduled to be updated with the above information. 

    Related Products

    This article applies to 2 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs
    Intel® Agilex™ 7 FPGAs and SoC FPGAs



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