Article ID: 000088978 Content Type: Troubleshooting Last Reviewed: 08/16/2023

Why do I see functional problems when simulating the 20.3 version of the Avalon® Streaming Single Clock FIFO Intel® FPGA IP in the Synopsys VCS simulator?

Environment

    Intel® Quartus® Prime Pro Edition
    Avalon-ST Single Clock FIFO Intel® FPGA IP
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Description

Due to the way that the Synopsys VCS simulator handles mixed language (VHDL and verilog) simulation, you may encounter functional errors when simulating the v20.3 and later version of the Avalon® Streaming Single Clock FIFO Intel® FPGA IP core.

Resolution

To work around this problem, add the -deraceclockdata VCS argument during simulation.

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This article applies to 1 products

Intel® Programmable Devices

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