Article ID: 000088862 Content Type: Errata Last Reviewed: 12/16/2021

Why do the values of the TLPBYPASS_ERR_STATUS status register of the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express persist after a system level warm reset?

Environment

  • Intel® Quartus® Prime Pro Edition
  • OS Independent family

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    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.3 and earlier, the values stored in the TLPBYPASS_ERR_STATUS status register of the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express will persist after a system warm reset (pin_perst event) or hot reset.

    A cold reset (power cycle) will clear the content of the TLPBYPASS_ERR_STATUS status register.

    Resolution

    To work around this problem, clear the TLPBYPASS_ERR_STATUS status register (offset 0x1310) after a warm reset using the Hard IP Reconfiguration Interface (pX_hip_reconfig_*).

    Please note that the Hard IP Reconfiguration Interface is 8-bit wide, making at least 3 write operations necessary to clear all the bits from the TLPBYPASS_ERR_STATUS status register. 

    This problem is scheduled to be fixed in a future Intel® Quartus® Prime Pro Edition Software release.

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs I-Series

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