Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.3, you may see this internal error when compiling a design that targets an Intel® Stratix® 10 device. This error occurs when there are no more LSM atoms available to reset the debug logic to a known state during power up.
To work around this problem, add an Intel® Configuration Reset Release Endpoint to Debug Logic IP from the Intel® Quartus® Prime Pro IP Catalog to the design. This means the IP must be created, added to the project, and instantiated in the design. This IP can be found in Intel® Quartus® Prime Pro by navigating in the IP Catalog to Library > Basic Functions > Simulation; Debug and Verification > Debug and Performance. Connect the conf_reset input of this IP to a post-configuration reset signal to ensure that debug logic on the device operates from a reliable initial state.
This problem is scheduled to be fixed in a future release of Intel® Quartus® Prime Pro Edition Software.