Article ID: 000088814 Content Type: Troubleshooting Last Reviewed: 01/10/2023

Why does the Lane Margining at Receiver feature of the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express report timing margin at maximum steps size for lanes under test?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software v21.4 and earlier, the timing margin reported by Lane Margining at Receiver feature of the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express is not accurate.

    Resolution

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 2 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs F-Series
    Intel® Agilex™ 7 FPGAs and SoC FPGAs I-Series

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.