Article ID: 000088754 Content Type: Troubleshooting Last Reviewed: 02/20/2023

Why do the signals tx_ex_delay_valid and rx_delay_valid of the CPRI Intel® FPGA IP core not read to clear as expected?

Environment

    CPRI
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in the CPRI Intel® FPGA IP core version 21.2 and earlier, you might see that the tx_ex_delay_valid and rx_ex_delay_valid operate as read only signals and do not  read to clear as descripted in the CPRI Intel® FPGA IP Core User Guide. 

Resolution

This problem is fixed starting with the Intel® Quartus® Prime Pro/Standard Edition Software version 21.3.

Related Products

This article applies to 3 products

Intel® Arria® 10 FPGAs and SoC FPGAs
Intel® Stratix® 10 FPGAs and SoC FPGAs
Intel Agilex® 7 FPGAs and SoC FPGAs

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