Article ID: 000088629 Content Type: Troubleshooting Last Reviewed: 11/23/2024

Why is the simulation result of the "demo_cfr" in the DSP Builder for FPGAs incorrect?

Environment

  • Intel® Quartus® Prime Pro Edition
  • DSP Builder for Intel® FPGAs Pro Edition
  • DSP Builder for Intel® FPGAs Pro Edition IPT-DSPBUILDER
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem with the DSP Builder for FPGAs in the Quartus® Prime Pro Edition Software v20.4, the .mdl simulink file only works for one specific device/speedgrade/clock target combination. The simulation results will be wrong with other combinations.

    Resolution

    To workaround this problem, replace the old .mdl simulink file in demo_cfr with the new demo_cfr.mdl file.

     

     

    Related Products

    This article applies to 6 products

    Intel Agilex® 7 FPGAs and SoC FPGAs
    Intel® Arria®
    Intel® Cyclone®
    Intel® MAX® 10 FPGAs
    MAX® V CPLDs
    Intel® Stratix®

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