Error(13452): Verilog HDL Module Instantiation error at pll_hdmi_reconfig.v(35): module "altera_pll_reconfig_top" has no parameter named "WAIT_FOR_LOCK".

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.3 and earlier, the error below will be seen when merging the HDMI Intel® Arria® 10 FPGA IP Design Example and the DisplayPort Intel® Arria® 10 FPGA IP Design Example into a single project.

 Error(13452): Verilog HDL Module Instantiation error at pll_hdmi_reconfig.v(35): module "altera_pll_reconfig_top" has no parameter named "WAIT_FOR_LOCK".

To work around this problem in current versions of the Intel® Quartus® Prime Design Software, please replace the library option from 'altera_pll_reconfig_XXX' to 'pll_hdmi_reconfig' in the pll_hdmi_reconfig.qip file.