Why does the testbench of the HDMI Intel® FPGA IP Design Example include the wrong Source General Control Packet (GCP) setting when fixed rate link (FRL) mode is disabled?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software v21.3 and earlier, the testbench of the HDMI Intel® FPGA IP design example has the wrong setting in the Source General Control Packet (GCP). This problem occurs when fixed-rate link (FRL) mode is disabled.

To work around this problem in current versions of the Intel® Quartus® Prime Edition Software, modify the ' tx_gcp_data' parameter from '{4'b1000, BPP}' to '{4'b0001, BPP}' in the file bitec_hdmi_tb.v.

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 22.1.