Why does the CPRI v7.0 Intel® FPGA IP core report timing violations on IP internal paths?

Due to a problem in the CPRI v7.0 Intel® FPGA IP core version 20.4 and earlier, you may see the timing violations within the CPRI v7.0 Intel® FPGA IP core itself. The timing violation paths in the Intel® Quartus® Prime Software Timing Analyzer are similar to those shown below:

from *inst_cpri_ii*reset_*synchronizer*sync_reset* to *inst_cpri_ii*

from *inst_c2p*reset_*synchronizer*sync_reset* to *inst_c2p*

The CPRI v7.0 Intel® FPGA IP core generates the required synchronization logic. However, the Synopsys Design Constraints Files (.sdc) do not correctly constrain these paths.

This problem is fixed starting with the Intel® Quartus® Prime Pro/Standard Edition Software version 21.1.