Article ID: 000088547 Content Type: Troubleshooting Last Reviewed: 12/16/2021

Error: Verilog HDL Module Instantiation error at bitec_hdmi_tx_aux_encoder.v(0): module "bitec_hdmi_aux_bch" has no parameter named "SYMBOL_PER_CLOCK"

Environment

  • Intel® Quartus® Prime Pro Edition
  • HDMI
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software v20.4,  you will see this error when integrating the HDMI Intel® FPGA IP 2.0 Tx and the HDMI Intel® FPGA IP 2.1 RX into a design.  This is because the module bitec_hdmi_aux_bch has the same module name between the HDMI Intel® FPGA IP 2.0 and the HDMI Intel® FPGA IP 2.1, but the parameters are different.

    Resolution

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software v21.3.

    Related Products

    This article applies to 2 products

    Intel® Arria® 10 FPGAs and SoC FPGAs
    Intel® Stratix® 10 FPGAs and SoC FPGAs

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