Article ID: 000088423 Content Type: Troubleshooting Last Reviewed: 11/18/2021

Why does my F-Tile PMA/FEC Direct PHY Intel® FPGA IP design fail to compile in the Support-Logic Generation stage when the design has at least one multiple PMA lanes variant with “Datapath clocking mode” set to “PMA” ?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Transceiver PHY
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software v21.3, when the design has at least one multiple PMA lanes variant with “Datapath clocking mode” set to “PMA”, it will fail to compile in the Support-Logic Generation stage with “Error (21842): Solver failed to find a solution” message.

    Resolution

    To work around this problem, replace your multiple PMA lanes variant with multiple instances of a 1-channel variant.
    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs

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