How do I view the row clock region boundaries in the Intel® Quartus® Prime Pro Edition Software?

The Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration says, "You cannot share a row clock between two PR regions" but it does not clearly specify how to view the row clock region boundaries in Intel® Quartus® Prime Pro Edition Software version.

For Intel® Arria® 10 devices and Intel® Cyclone® 10 GX devices, follow these steps:

1. Click Tools > Chip Planner.
2. In Chip Planner, click the Layers tab and select the Basic layer.
3. Check Spine Clock Region; you will see the spine clock region boundaries.
4. A row clock region is half-spine clock wide (divided by the dotted line) and one LAB row tall.

For Intel® Stratix® 10 devices and Intel Agilex® devices, follow these steps:

1. Click Tools > Chip Planner.
2. In Chip Planner, click the Layers tab and select the Basic layer.
3. Check Clock Sector Region; you will see the clock sector region boundaries.
4. A row clock region is half-clock sector-wide (divided by the dotted line) and one LAB row tall.