Article ID: 000088369 Content Type: Troubleshooting Last Reviewed: 04/13/2023

Why does dmatest fail when test_buf_size is changed to a larger value when Intel® Stratix® 10 SoC FPGA or Intel Agilex® 7 SoC FPGA is used?

Environment

    Intel® Quartus® Prime Pro Edition
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Description

When running dmatest for DMAC in Intel® Stratix® 10 SoC FPGA or Intel Agilex® 7 SoC FPGA, you might find the following error when changing the test_buf_size to a larger value (the default value of test_buf_size is 16 KB):

root@agilex:~# echo 1 > /sys/module/dmatest/parameters/run 

[  149.931113] dmatest: No channels configured, continue with any 

[  149.937236] dmatest: Added 1 threads using dma0chan0 

[  149.942349] dmatest: Started 1 threads using dma0chan0 

root@agilex:~# [  149.963288] dma-pl330 ffda0000.pdma: swiotlb buffer is full (sz: 2097152 bytes), total 32768 (slots), used 1024 (slots) 

[  149.974096] dma-pl330 ffda0000.pdma: overflow 0x00000003ebc00000+2097152 of DMA mask ffffffff bus mask 0 

[  149.983622] ------------[ cut here ]------------ 

Resolution

The root cause is that DMAC 330 has only 32-bit address width; the SWIOTLB default buffer size is not enough for DMAC 330 to access the whole range of DDR.

To work around this problem, you can use one of the following solutions:

  1. Configure Linux to use only the first 2 GB of DDR; DMAC can access the 2 GB memory range with a 32-bit width address so the SWIOTLB buffer is not required to increase. 
  2. Modify the kernel source and U-boot command line to make the SWIOTLB buffer larger:

In /include/linux/swiotlb.h, change IO_TLB_SEGSIZE to a larger number (should be a power of2); for example, #define IO_TLB_SEGSIZE 1024

Change U-boot environment to add customized swiotlb value; for example,  setenv bootargs earlycon console=ttyPS0,115200 swiotlb=32768

Related Products

This article applies to 2 products

Intel Agilex® 7 FPGAs and SoC FPGAs
Intel® Stratix® 10 FPGAs and SoC FPGAs

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