Article ID: 000088120 Content Type: Compatibility Last Reviewed: 12/13/2021

Why does the DisplayPort Intel® Stratix® 10 FPGA IP Design Example fail RX link training at High Bit Rate 3 (HBR3)?

Environment

  • Intel® Quartus® Prime Pro Edition
  • DisplayPort
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the DisplayPort Intel® Stratix® 10 FPGA IP Design Example generated with the Intel® Quartus® Prime Design Software versions 20.3 and earlier, you may observe RX link training failure at HBR3 and the link down trains to HBR2.

    Resolution

    To workaround this problem in the Intel® Quartus® Prime Pro Edition Software version 20.3 and earlier, follow the steps:

    1. Replace ./rtl/rx_phy/rx_phy_top.v with rx_phy_top.v

    2. Replace ./rtl/tx_phy/tx_phy_top.v with tx_phy_top.v

    3. Replace ./rtl/bitec_reconfig_alt_s10.v with intel_reconfig_alt_s10.v

    This problem is fixed in the Intel® Quartus® Prime Pro Edition Software version 20.4 and later.

    Related Products

    This article applies to 6 products

    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 SX SoC FPGA
    Intel® Stratix® 10 TX FPGA
    Intel® Stratix® 10 GX Development Kit DK-DEV-1SGX-H-A
    Intel® Stratix® 10 GX Development Kit DK-DEV-1SGX-L-A
    Intel® Stratix® 10 GX FPGA

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