Why does the DisplayPort Intel® Stratix® 10 FPGA IP Design Example fail RX link training at High Bit Rate 3 (HBR3)?

Due to a problem in the DisplayPort Intel® Stratix® 10 FPGA IP Design Example generated with the Intel® Quartus® Prime Design Software versions 20.3 and earlier, you may observe RX link training failure at HBR3 and the link down trains to HBR2.

To workaround this problem in the Intel® Quartus® Prime Pro Edition Software version 20.3 and earlier, follow the steps:

1. Replace ./rtl/rx_phy/rx_phy_top.v with rx_phy_top.v

2. Replace ./rtl/tx_phy/tx_phy_top.v with tx_phy_top.v

3. Replace ./rtl/bitec_reconfig_alt_s10.v with intel_reconfig_alt_s10.v

This problem is fixed in the Intel® Quartus® Prime Pro Edition Software version 20.4 and later.