Due to a problem in the Intel® Quartus® Prime Pro Edition Software v21.1, the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express may fail to initialize the TX interface logic out of reset.
As a result, the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express TX interface will not be initialized correctly and will not be able to transmit Transaction Layer Packets (TLPs).
To work around this problem, add the following assignments to the Intel® Quartus® Prime Software Settings File (QSF):
set_instance_assignment -name SYNCHRONIZER_IDENTIFICATION FORCED -to *|rnr_pcie_reset_ctrl_inst|p0_pld_link_req_rst_reg
set_instance_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 1 -to *|rnr_pcie_reset_ctrl_inst|p0_pld_link_req_rst_reg
This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software v21.3.
