Article ID: 000088050 Content Type: Troubleshooting Last Reviewed: 11/24/2021

Why does U-boot SPL get stuck when warm reset triggered continuously?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Intel® SoC FPGA Embedded Development Suite (SoC EDS) Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the U-boot SPL version 2020.10 and earlier, when warm reset is triggered continuously, U-boot SPL might be stuck at the below message:

    U-Boot SPL 2020.10 (Jul 01 2021 - 14:23:45 +0800)
    Reset state: Warm (Triggered by Watchdog 0)
    MPU         1000000 kHz
    L3 main     400000 kHz
    Main VCO    2000000 kHz
    Per VCO     2000000 kHz
    EOSC1       25000 kHz
    HPS MMC     50000 kHz
    UART        100000 kHz
    DDR: 4096 MiB

    This problem only happens after triggering thousands of warm resets and sometimes it would not happen at all.

     

    Resolution

    There is no fix for this problem right now.

    Related Products

    This article applies to 2 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs
    Intel® Stratix® 10 FPGAs and SoC FPGAs

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