Due to a problem in the Intel® Quartus® Prime Standard Edition Software version 20.1 and earlier, you may find that the parentheses are removed when you create a symbol from your Verilog HDL/VHDL file. This is because during synthesis, the Intel® Quartus® Prime Standard Edition Software parses the code into a string which does not preserve the parentheses.
An example code that can result into this problem:
module example#(
parameter integer parameter_1 = 4,
parameter integer parameter_2 =2,
parameter integer parameter_3 = 8
)
(
input clk,
input rst,
output logic [((parameter_1 * ( parameter_2 + parameter_3 )) - 1) : 0] word_o);
During synthesis the output logic word_o will be parsed as the following string in the .bsf file:
[parameter_1 * parameter_2 + parameter_3 - 1 : 0]
To work around this problem, edit the generated symbol on the block design file using a text editor to include the parentheses.
This problem is fixed starting with the Intel® Quartus® Prime Standard Edition Software version 21.1.