In the Quartus® Prime Pro Edition Software v21.3 and earlier, you may see this error when compiling designs that include the LVDS SERDES FPGA IP in external phase-locked loop (PLL) mode.
This error occurs when the LVDS SERDES FPGA IP is listed above the IOPLL FPGA IP in the Quartus® Settings File (QSF).
To avoid this error, make sure the IOPLL FPGA IP is listed above the LVDS SERDES FPGA IP in the Quartus® Settings File (QSF).
A more helpful error message is scheduled to be added to a future release of the Quartus® Prime Pro Edition Software.