Article ID: 000087789 Content Type: Error Messages Last Reviewed: 04/18/2022

Why does my design fail to pass the Intel® Quartus® Prime Pro Edition Software “Support Logic Generation” phase when using a combination of the F-Tile Ethernet Intel® FPGA Hard IP with PTP variant and an F-Tile PMA Direct PHY variant?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.2, the combination of an F-Tile Ethernet Intel® FPGA Hard IP with PTP variant and an F-Tile PMA Direct PHY variant will fail to pass the Intel® Quartus® Prime Pro “Support Logic Generationphase with the following error message: “Error (21842): Solver failed to find a solution”.

    Resolution

    To work around this problem in Intel® Quartus® Prime Pro Edition Software version 21.2 perform the following steps:

    1. Navigate to the <pma_direct_variant>/synth directory.
    2. Open the “directphy_f_hip.sv” file.
    3. Change the following lines FROM:

    a. localparam  local_bb_f_ehip_e400g_ptp0_aib2_div2_clk = bb_f_ehip_e400g_ptp0_aib2_div2_clk;

    b. localparam  local_bb_f_ehip_e400g_ptp1_aib2_div2_clk = bb_f_ehip_e400g_ptp1_aib2_div2_clk;

    TO:

    a. localparam  local_bb_f_ehip_e400g_ptp0_aib2_div2_clk = "__BB_DONT_CARE__"; 

    b. localparam  local_bb_f_ehip_e400g_ptp1_aib2_div2_clk = "__BB_DONT_CARE__";  

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 21.4.

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs I-Series

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.