Article ID: 000087757 Content Type: Errata Last Reviewed: 09/04/2023

Why is the o_rx_pcs_fully_aligned signal not asserted in my F-tile Ethernet Intel® FPGA Hard IP simulation in Questa* Intel® FPGA Edition when IEEE* 1588 PTP, or Auto-negotiation (AN) and Link training (LT), or both features are enabled?

Environment

  • Intel® Quartus® Prime Pro Edition
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    Critical Issue

    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.3, the F-Tile Ethernet Intel® FPGA Hard IP does not configure the Questa* Intel® FPGA Edition simulation environment properly.

    The F-Tile Ethernet Intel® FPGA Hard IP requires macro definition support for environment setup, which the Questa* Intel® FPGA Edition simulator doesn't have.

    As a result, the o_rx_pcs_fully_aligned signal is not asserted, and the simulation cannot complete the RX reset sequence.

     

     

     

    Resolution

    You can run F-Tile Ethernet Intel® FPGA Hard IP PTP simulations with Questa* Intel® FPGA Edition simulation OEM starting with Intel® Quartus® Prime Pro Edition Software version 22.1.

     

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs I-Series