Article ID: 000087757 Content Type: Errata Last Reviewed: 10/06/2021

Why is the o_rx_pcs_fully_aligned signal not asserted in my F-tile Ethernet Intel® FPGA Hard IP simulation in Questa* Intel® FPGA Edition when IEEE* 1588 PTP, or Auto-negotiation (AN) and Link training (LT), or both features are enabled?

Environment

  • Intel® Quartus® Prime Pro Edition
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    Critical Issue

    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.3, the F-Tile Ethernet Intel® FPGA Hard IP do not configure the Questa* Intel® FPGA Edition simulation environment properly.

     

    The F-Tile Ethernet Intel® FPGA Hard IP requires macro definition support for environment setup, which the Questa* Intel® FPGA Edition simulator doesn't have.

     

    As a result, the o_rx_pcs_fully_aligned signal is not asserted and the simulation is unable to complete the RX reset sequence.

    Resolution

    To work around this problem, use a simulation software with macro definition support such as VCS* or Modelsim* or the full edition of Questa* for the F-tile Ethernet Intel® FPGA Hard IP simulation with IEEE 1588 PTP enabled.

     

    For instructions on how setup the macro definition for the F-tile Ethernet Intel® FPGA Hard IP refer to the Why is the o_rx_pcs_fully_aligned signal not asserted in my F-Tile Ethernet Intel® FPGA Hard IP simulation when IEEE 1588 PTP and FEC are enabled? article in the Intel® FPGA Knowledge Base.

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs I-Series

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