Article ID: 000087752 Content Type: Errata Last Reviewed: 04/18/2022

Why are TLPs being lost when using the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express?

Environment

  • Intel® Quartus® Prime Pro Edition
  • PCI Express
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    Critical Issue

    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software v21.2, the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express may fail to capture the pX_tx_st_eop_i signal assertion from the application logic at the Avalon® Streaming TX interface.

    As a result, the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express will drop the Avalon® Streaming packet and will not generate the corresponding Transaction Layer Packet (TLP).

    The following Avalon® Streaming packet delivered to the Avalon® Streaming TX interface may not be affected by this problem.

    Resolution

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software v21.3.

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs I-Series

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