Article ID: 000087743 Content Type: Troubleshooting Last Reviewed: 09/29/2021

Which signal of the Intel® Stratix® 10 High Bandwidth Memory (HBM2) Interface Intel® FPGA IP should be used to determine when it's safe to start interacting with the AXI bus interface?

Environment

  • Intel® Quartus® Prime Pro Edition
  • High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
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    Description

    When using the Intel® Stratix® 10 High Bandwidth Memory (HBM2) Interface Intel® FPGA IP, you may see the AXI wready signal getting asserted during calibration but it is not safe to interact yet. You should wait until the local_cal_success signal gets asserted before you start interacting with the AXI bus interface.

    Resolution

    This information will be included in a future release of the Intel® Stratix® 10 High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide.

    Related Products

    This article applies to 2 products

    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 NX FPGA

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